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parameter MB15U36 rf frequency of operation, max. 2.0 ghz if/rf frequency of operation, max 1.2 ghz low power supply voltage 3 - 5.5v low power supply current 6.0 ma @ 3v prescaler divide ratios rf1, rf2 = 64/65 or 128/129 power-saving function 10a typical MB15U36 dual pll frequency synthesizer with on-chip prescaler packages 18-bit programmable divider: ? binary 7-bit swallow counter: 0 to 127 ? binary 11-bit programmable counter: 3 to 2047 software selectable charge pump current: ? do output 1.0 or 4.0 ma @ v cc =3v evaluation kits available description the fujitsu MB15U36 dual pll is a serial input frequency synthesizer with 2.0 ghz and 1.2 ghz prescalers. the prescalers both have a selectable dual modulus division ratio of 64/65 or 128/129 enabling pulse swallow operation. the MB15U36 utilizes a refined charge pump design (fujitsu?s super charger)that provides fast tuning along with low spurious noise and phase noise characteristics. the MB15U36 is ideally suited for digital mobile communications, including gsm, dcs1800, pcs1900, is-136, is-95 and ism-band applications. features very low spurious and phase noise characteristics wide operating voltage: 3.0 to 5.5 volts low operating current: 6.0 ma @ v cc = 3 volts (typical) power-saving current: 10a (typical) wide operating temperature: ?40 to +85c plastic 20-pin ssop package reference counter: ? 15-bit programmable divider: 3 to 32767 20-pin plastic ssop, fpt-20p-m03

MB15U36 fujitsu microelectronics, inc. 3 table of contents pin descriptions: MB15U36........................................................................................................ ........................................... 4 block diagram: MB15U36........................................................................................................... .......................................... 5 absolute maximum ratings ......................................................................................................... ........................................... 6 recommended operating conditions................................................................................................. ....................................... 6 handling precautions............................................................................................................ .......................................... 6 electrical characteristics...................................................................................................... .................................................. 7 measurement circuit (fin, osc in input sensitivity) .............................................................................................................. ...... 9 typical electrical characteristics ............................................................................................... ............................................ 10 reference information ........................................................................................................... ........................................ 13 functional descriptions ......................................................................................................... .............................................. 14 serial data input ................................................................................................................ .......................................... 14 table 1: control bits ............................................................................................................. ........................................ 14 shift register configuration for the programmable reference counter ................................................................... ....... 14 shift register configuration for the programmable counter ............................................................................ ............ 15 table 2: binary 14-bit programmable reference c ounter data setting................................................................................. 15 table 3: phase comparator phase switching data setting................................................................................ .................. 15 table 4: charge pump current setting ................................................................................................ ............................ 16 table 5: charge pump output impedance setting ........................................................................................ ..................... 16 table 6: ld/f out output select data setting........................................................................................................ ............ 16 table 7: binary 11-bit programmable counter data setting.............................................................................. ................. 16 table 8: binary 7-bit swallow counter data setting .................................................................................... ..................... 17 table 9: prescaler data setting .................................................................................................... .................................. 17 power saving mode (intermittent mode control circuit) ................................................................................ ........................ 17 table 10: power save internal shutdown logic......................................................................................... ......................... 17 serial data input timing .......................................................................................................... ........................................... 18 table 11: timing parameters....................................................................................................... ................................... 18 power-on timing diagram .......................................................................................................... ................................. 18 phase detector output waveform .................................................................................................... ...................................... 19 application example ............................................................................................................. .............................................. 20 application example: fastlock mode ................................................................................................ ..................................... 21 ordering information ............................................................................................................ .............................................. 22 package dimensions .............................................................................................................. ............................................. 23
dual pll frequency synthesizer with on-chip prescaler 4 fujitsu microelectronics, inc. pin descriptions: MB15U36 pin no. pin name i/o descriptions ssop 1vcc 1 ? power supply voltage input pin for the rf1-pll section, the shift register, and the oscillator input buffer. when poweris off, latched data for rf1-pll is lost. 2vp 1 i power supply for the rf1-pll charge pump. (independent of pin 19) 3do 1 o charge pump output for the rf1-pll section. phase detector characteristics can be reversed using the fc-bit. 4 gnd1 ? ground for the rf1-pll section. 5 fin 1 i prescaler input for the rf1-pll. connection to an external vco should be via ac coupling. 6xfin 1 i prescaler complimentary input for the rf1-pll section. this pin should be grounded via a small capacitor. 7 gnd1 ? ground for the rf1-pll section. 8osc in i external tcxo reference oscillator input or connection to crystal. tcxo should be connected via ac c oupling. 9osc out o oscillator output or connection to crystal. 10 ld/f out o lock detect signal output (ld) or phase comparator monitoring output (f out ). the output signal is selected by the lds and fds bits in the serial programming data. 11 clock i clock input for the 22-bit shift register. one bit of data is shifted into the shift register on a rising edge of the clock. 12 data i serial data input. data is transferred to the corresponding latch (rf1-ref counter, rf1-prog. counter, rf2-ref. counter, rf2-prog. counter) according to the control bits settings in the serial programming data. 13 le i load enable signal input. when the le bit is set to ?h?, data in the shift register is transferred to the corresponding latch ac cording to the control bits settings in the serial programming data. 14 gnd2 ? ground for the rf2-pll section. 15 xfin 2 i prescaler complimentary input for the rf2-pll section. this pin should be grounded via a small capacitor. 16 fin 2 i prescaler input for the rf2-pll. connection to an external vco should be via ac coupling. 17 gnd2 ? ground for the rf2-pll section. 18 do 2 o charge pump output for the rf2-pll section. phase detector characteristics can be reversed using the fc-bit. 19 vp 2 i power supply for the rf2-pll charge pump. (independent of pin 2) 20 vcc 2 ? power supply voltage input pin for the rf2-pll section. when power is off, latched data for rf2-pll is lost. (fpt-20p-m03) vcc 1 vp 1 do 1 gnd 1 fin 1 xfin 1 gnd 1 osc in le data clock 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 top view 9 10 20 19 osc out ld/f out gnd 2 fin 2 xfin 2 gnd 2 do 2 vcc 2 vp 2
MB15U36 fujitsu microelectronics, inc. 5 block diagram: MB15U36 11 clock 12 data 13 le 6 xfin 1 fin 1 osc in fin 2 2-bit latch 7-bit latch 11-bit latch 2-bit latch latch selector 22-bit shift register 7-bit latch 11-bit latch phase comp. (rf2-pll) lock detect (rf2-pll) lock detect (rf1-pll) charge pump (rf2-pll) phase comp. (rf1-pll) charge pump (rf1-pll) 5-bit latch 15-bit latch binary 7-bit swallow counter (rf2-pll) binary 15-bit programmable ref. counter (rf2-pll) binary 11-bit programmable counter (rf2-pll) binary 7-bit swallow counter (rf1-pll) binary 11-bit programmable counter (rf1-pll) prescaler (rf2-pll) 64/65, 128/129 prescaler (rf1-pll) 64/65, 128/129 ps sw v cc 2 gnd 2 20 14 fp rf2 18 do 2 ld rf2 selector 3 do 1 or 10 ld/fout fp rf1 fr rf1 c n 1 c n 2 fr rf2 fr rf1 fp rf2 fp rf1 vcc 1 gnd 2 16 8 1 4 fc cmc zc lds fds 15-bit latch binary 15-bit programmable ref. counter (rf1-pll) 5-bit latch fc cmc zc lds fds ld rf2 ld rf1 ps sw 9 5 17 ld rf1 7 fr rf2 osc out 2 vp 1 19 vp 2 xfin 2 15
dual pll frequency synthesizer with on-chip prescaler 6 fujitsu microelectronics, inc. absolute maximum ratings warning: semiconductor devices can be permanently damaged by the application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions *1: prescaler divide ratio is only 64/65 (sw = ?l?) at rf1. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the device?s electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability an d could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not repr esented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative befor ehand. handling precautions this device should be transported and stored in anti-static containers this is a static-sensitive device; take proper anti-esd precautions. ensure that personnel and equipment are properly grounded. cover workbenches with grounded conductive mats. always turn the power supply off before inserting or removing the device from its socket. protect leads with a conductive sheet when handling or transporting pc boards with devices. parameter symbol rating unit note power supply voltage vcc 1,2 ?0.5 to +6.5 v vp 1,2 ?0.5 to +6.5 v input voltage v i ?0.5 to +6.5 v output voltage v o ?0.5 to +6.5 v storage temperature t stg ?55 to +125 c parameter symbol value unit note min. typ. max. power supply voltage vcc 3.0 5.0 5.5 v vcc 1 =vcc 2 vp 3.0 5.0 5.5 v vcc 1 =vcc 2 *1 input voltage v i gnd ? v cc v operating temperature ta ?40 ? +85 c
MB15U36 fujitsu microelectronics, inc. 7 electrical characteristics (v cc =3.0 to 5.5v,ta = ?40 to +85c) parameter symbol condition value unit min. typ. max. power supply current icc1 *1 fin 1 = 2000 mhz fosc=12mhz vcc = 5v ? 6.0 ? ma vcc = 3v ? 3.5 ? ma icc2 *2 fin 2 = 1200 mhz fosc=12mhz vcc = 5v ? 3.0 ? ma vcc = 3v ? 2.5 ? ma power saving current ips 1 vcc1 current at ps bit rf1, rf2 =?h? ? 0.1 *3 10 a ips 2 vcc1 current at ps bit rf2 =?h? ? 0.1 *3 10 a operating frequency fin 1 *4 rf1-pll 100 ? 2000 mhz fin 2 *4 rf2-pll 50 ? 1200 mhz f osc 500mvp-p minimm 3 ? 40 mhz input sensitivity fin rf1-pll pfin rf1- pll 50 ? load system (refer to measurement circuit.) ?10 ? +2 dbm fin rf2-pll pfin rf2-pll 50 ? load system (refer to measurement circuit.) ?10 ? +2 dbm osc in v osc 0.5 ? v cc vp-p input voltage data, clock, le v ih v cc 0.8 ? ? v v il ??v cc 0.2 input current data, clock, le i ih *5 v ih = vcc ?1.0 ? +1.0 a i il *5 v il = vcc ?1.0 ? +1.0 osc in i ih v ih = vcc 0 ? +100 a i il *5 v il =vcc ?100 ? 0 output voltage ld/f out v oh i oh =?1ma vcc?0.4 ? ? v v ol i ol =1ma ? ? 0.4 do 1 ,do 2 v doh i oh =?0.5ma vcc?0.4 ? ? v v dol i ol =0.5ma ? ? 0.4 high impedance cutoff current do 1 ,do 2 i off v cc =vp=5.0v 0.5v v do vp ? 0.5v ??3.0na output current ld/f out i oh *5 v cc =5.0v ?1.0 ? ? ma i ol v cc =5.0v ??1.0ma do 1 ,do 2 i doh *5 v cc =vp=5.0v cmc bit = ?l? ? ?1.25 ? ma v cc =vp=3.0v cmc bit = ?l? ? ?1.0 ? ma i dol v cc =vp=5.0v cmc bit = ?l? ? 1.25 ? ma v cc =vp=3.0v cmc bit = ?l? ? 1.0 ? ma i doh *5 v cc =vp=5.0v cmc bit = ?h? ? ?5.0 ? ma v cc =vp=3.0v cmc bit = ?h? ? ?4.0 ? ma i dol v cc =vp=5.0v cmc bit = ?h? ? 5.0 ? ma v cc =3.0v cmc bit = ?h? ? 4.0 ? ma
dual pll frequency synthesizer with on-chip prescaler 8 fujitsu microelectronics, inc. *1: conditions: vcc 1 =5.0v,ta=+25 c, in locking state. *2: conditions: vcc 2 =5.0v,ta=+25 c, in locking state. *3: conditions: vcc = 5.0v, fosc = 12.8mhz (-2dbm),ta = +25 c *4: ac coupling, 1000pf capacitor is connected under the condition of min. operating frequency. *5: the symbol ??? (minus) means direction of current flow. *6: v cc =5.0v,ta=+25 c(|i 3 |?|i 4 |)/[(|i 3 |+|i 4 |)/2] x 100(%) *7: v cc =5.0v,ta=+25 c[(|i 2 |?|i 1 |)/2]/[(|i 1 |+|i 2 |)/2] x 100(%) (applied to each i dol ,i doh ) *8: v cc =5.0v, [|i do(85 c) ?i do(?40 c) |/2]/[|i do(85 c) +i do(?40 c) |/2]x100(%)(appliedtoeachi dol ,i doh ) charge pump current characteristics i dol /i doh i domt *6 v do =v cc /2 ?3?% i do vs v do i dovd *7 0.5v v do v cc ?0.5v ?15?% i do vs ta i dota *8 ?40c ta +85 c, v do = vp/2 ?10?% parameter symbol condition value unit min. typ. max. i 1 i 1 i 3 i 2 i 2 i 4 i dol i doh 0.5 vcc/2 vcc vcc ? 0.5 v charge pump output voltage (v)
MB15U36 fujitsu microelectronics, inc. 9 measurement circuit (for measuring input sensitivity of fin and oscin) 1000 pf 1000 pf from controller osc in xfin 1 98765432 12 13 14 15 16 17 18 19 fin 1 osc out gnd 1 gnd 1 do 1 vp 1 1000 pf le xfin 2 fin 2 data gnd 2 gnd 2 do 2 vp 2 MB15U36 1 20 10 11 vcc 1 ld/f out clock vcc 2 .1 f .1 f .1 f .1 f oscilloscope 1000 pf sig. gen. sig. gen. 1000 pf sig. gen. 50 50 ? ? ? 50 f out
dual pll frequency synthesizer with on-chip prescaler 10 fujitsu microelectronics, inc. typical electrical characteristics: MB15U36 vfinrf2 vs. finrf2 -50 -40 -30 -20 -10 0 10 0 500 1000 1500 2000 finrf2 [mhz] vfinrf2 [dbm] vfin[dbm]@5.5v vfin[dbm]@5.0v vfin[dbm]@4.5v vfin[dbm]@3.0v vfinrf1 vs. finrf1 -50 -40 -30 -20 -10 0 10 0 500 1000 1500 2000 2500 3000 finrf1 [mhz] vfinrf1 [dbm] vfin[dbm]@5.5v vfin[dbm]@5.0v vfin[dbm]@4.5v vfin[dbm]@3.0v input sensivity of fin (rf1) versus input frequency input sensivity of osc in versus input frequency input sensivity of fin (rf2) versus input frequency pfin rf1 vs. fin rf1 pfin rf1 (dbm) pfin(dbm )@ 5.5v pfin(dbm)@5.0v pfin(dbm)@4.5v pfin(dbm)@3.0v pfin(dbm)@5.5v pfin(dbm)@5.0v pfin(dbm)@4.5v pfin(dbm)@3.0v spec spec fin rf1 (mhz) pfin rf2 vs. fin rf2 pfin rf2 (dbm ) fin rf2 (mhz) vfosc vs. fosc -50 -40 -30 -20 -10 0 10 0 50 100 150 200 250 fosc [mhz] vosc [dbm] voscin[dbm]@5.5v voscin[dbm]@5.0v voscin[dbm]@4.5v voscin[dbm]@3.0v spec p osc (dbm )@ 5.5v p osc (dbm)@5.0v p osc (dbm)@4.5v p osc (dbm)@3.0v pfin osc vs. fin rf2 pfin osc (dbm )
MB15U36 fujitsu microelectronics, inc. 11 typical electrical characteristics: MB15U36 conditions: ta = +25 c do output current: 1 x do mode id o l vs. vdo l 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 00.511.522.53 vcc =5v vcc =3v ?l? level output voltage o ? ?d ?? id o l(m a) ?l? level output voltage vdol ( v ido h vs. vdo h 0 1 2 3 4 5 6 7 8 -3 -2.5 -2 -1.5 -1 -0.5 0 vcc=5v vcc=3v ?h? level output voltage idoh (ma) ?h? level output voltage vdoh ( v ?h? level output voltage v doh (v) ?h? level output current i doh (ma) i doh -v doh ?l? level output voltage v dol (v) ?l? level output current i dol (ma) i dol -v dol
dual pll frequency synthesizer with on-chip prescaler 12 fujitsu microelectronics, inc. typical electrical characteristics: MB15U36 conditions: ta = +25 c do output current: 4 x do mode ido h vs. vdo h 0 1 2 3 4 5 6 7 8 -8 -7 -6 -5 -4 -3 -2 -1 0 vcc=5v vcc=3v ?h? level output voltage idoh (ma) "h? level output voltage vdoh ( v id o l vs . vd o l 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 012345678 vcc=5v vcc=3v ?l? level output voltage idol (ma) ?l? level output voltage vdol ( v ?h? level output voltage v doh (v) ?h? level output current i doh (ma) i doh -v doh ?l? level output voltage v dol (v) ?l? level output current i dol (ma) i dol -v dol
MB15U36 fujitsu microelectronics, inc. 13 reference information: MB15U36 (1760.000 mhz 1800 .000 mhz, within 1khz) typical plots measure with the test circuit are shown below. each plot shows lock up time, phase noise, and reference leakage. -80.3 dbc rfplllockuptime=387 s (1800.000 mhz 1760 .000 mhz, within 1khz) rf pll lock up time = 442 s rf pll phase noise @ max within loop band = -66.5 dbc/hz rf pll reference leakage @ 200 khz offset = -80.3 dbc sg spectrum analyzer osc in fin do lpf vco test circuit f vco = 1780 mhz k v = 58 mhz/v fr = 200 khz f osc =10mhz v cc =v p = 3.0v v vco = 5.0v ta = +25 c cp: 1ma mode 3.3k ? 6800 ? 6800pf 150pf 750pf lpf
dual pll frequency synthesizer with on-chip prescaler 14 fujitsu microelectronics, inc. functional descriptions the vco output frequency can be calculated using the following equation: f vco ={(mxn)+a}xf osc r(a MB15U36 fujitsu microelectronics, inc. 15 functional descriptions table 2. binary 15-bit programmable reference counter data setting note: divide ratio less than 3 is prohibited. table 3. phase comparator phase switching data setting notes: 1) z = high-impedance 2) the fc bit should be set depending upon the vco and lpf polarity divide ratio (r) r 15 r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 3 000000000000011 4 000000000000100 . ............... 32767111111111111111 do rf1-pll,rf2-pll fc rf1-pll,rf2-pll = ?h? fc rf1-pll,rf2-pll = ?l? fr > fp h l fr = fp z z fr < fp l h vco polarity (1) (2) cnt1, 2 control bits [table 1] n1 to n11 divide ratio setting bits for the programmable counter (3 to 2,047) [table 7] a1 to a7 divide ratio setting bits for the swallow counter (0 to 127) [table 8] sw divide ratio setting bit for the prescalers [table 9] (64/65 or 128/129 for the rf1-pll and rf2-pll) ps power saving mode c ontrol bit [table 10] note: input data with msb first. programmable counter c n 1 1 2 3 4 a 1 5 a 2 6 a 3 7 a 4 8 a 5 9 a 6 10 a 7 11 n 1 12 n 2 13 n 3 14 n 4 15 n 5 16 n 6 17 lsb msb data flow c n 2 18 n 7 n 8 19 n 9 20 n 10 21 n 11 22 s w p s vco input voltage vco output frequency (1) (2)
dual pll frequency synthesizer with on-chip prescaler 16 fujitsu microelectronics, inc. functional descriptions table 4. charge pump current setting (cmc) table 5. charge pump output impedance setting (zc) table 6. ld/fout output select data setting note: x = don?t care table 7. binary 11-bit programmable counter data setting note: divide ratio less than 3 is prohibited. cmc current value l1xdo h4xdo zc do output impedance l normal output h high impedance lds rf1 lds rf2 fds rf1 fds rf2 ld/f out output signal l l l l disabled l h l l ld signal (rf2 lock detect) h l l l ld signal (rf1 lock detect) h h l l ld signal (rf1/rf2 lock detect) xllhf out (output fr rf2 ) xlhlf out (output fr rf1 ) xhlhf out (output fp rf2 ) xhhlf out (output fp rf2 ) l l h h fastlock l h h h rf2 counter reset h l h h rf1 counter reset h h h h rf1/rf2 counter reset divide ratio (n) n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 3 00000000011 4 00000000100 . ........... 2047 11111111111
MB15U36 fujitsu microelectronics, inc. 17 functional descriptions table 8. binary 7-bit swallow counter data setting note: divide ratio (a) range = 0 to 127 table 9. prescaler data setting (sw) power-saving mode (intermittent mode control) the intermittent mode control circuit greatly reduces the pll power consumption by shuting down various internal functions, as shown in table 10, depending upon the settings of the power save (ps) bits. setting the ps bits to ?h? enters the corresponding pll into the power-saving mode. see the electrical characteristics chart for the specific value of current when in the power-saving mode. the phase detector output, do, becomes high impedance. serial data can be entered while in the power-saving mode. setting the ps pins ?l? releases the power-saving mode, returning the selected pll to normal operation. note: when power (v cc ) is first applied, the device must be in standby mode, ps = high, for at least 1 s. table 10. power save internal shutdown logic (ps) divide ratio (a) a 7 a 6 a 5 a 4 a 3 a 2 a 1 0 0000000 1 0000001 . ....... 127 1111111 prescaler divide ratio sw = ?l? sw = ?h? rf1-pll 64/65 128/129 rf2-pll 64/65 128/129 ps rf2 ps rf1 rf2-pll counters rf1-pll counters osc input buffer h h off off off l h on off on hl off on on l l on on on
dual pll frequency synthesizer with on-chip prescaler 18 fujitsu microelectronics, inc. serial data input timing lsb msb 1st data 2nd data control bit invalid data clock data le t 7 t 1 t 2 t 3 t 4 t 5 t 6 table 11. timing parameters notes: 1) on the rising edge of the clock, one bit of the data is transferred into the shift register. 2) le should be set to ?l? when the data is transferred into the shift register. parameter min. typ. max. unit parameter min. typ. max. unit t1 20 ? ? ns t5 100 ? ? ns t2 20 ? ? ns t6 20 ? ? ns t3 30 ? ? ns t7 100 ? ? ns t4 30 ? ? ns power-on timing (1) ps = h (power-saving mode) at power-on (2) input serial data 1 s later after power supply remains stable (v cc > 2.2v). (3) release power-saving mode (ps: h ? l) 100ns later after setting serial data. on off v cc clock data le ps (1) (2) (3) t v 1 s t ps 100 ns
MB15U36 fujitsu microelectronics, inc. 19 phase detector output waveform notes: 1) phase error detection range: ?2 to +2 2) pulses on do signal during locked state are output to prevent dead zone. t wu fr rf1-pll, rf2-pll fp rf1-pll, rf2-pll t wl ld (fc bit = ?h?) do rf1-pll, rf2-pll z l (fc bit = ?l?) z h do rf1-pll, rf2-pll
dual pll frequency synthesizer with on-chip prescaler 20 fujitsu microelectronics, inc. application example vco lpf tcxo 3v 1000 pf output 1000 pf from controller osc in xfin 1 98765432 12 13 14 15 16 17 18 19 fin 1 osc out gnd 1 gnd 1 do 1 vp 1 3v 1000 pf vco lpf output le xfin 2 fin 2 data gnd 2 gnd 2 do 2 vp 2 MB15U36 1 20 10 11 vcc 1 ld/f out clock vcc 2 1000 pf 3v 3v lock detect .1 f .1 f .1 f .1 f 1000 pf notes: 1) package type: 20-pin ssop 2) clock, data, le: insert a pull-down or pull-up resistor as needed to prevent oscillation when the terminals are left open.
MB15U36 fujitsu microelectronics, inc. 21 application example: fastlock mode lpf tcxo 3v 1000 pf output 1000 pf from controller osc in xfin 1 98765432 12 13 14 15 16 17 18 19 fin 1 osc out gnd 1 gnd 1 do 1 vp 1 3v 1000 pf vco lpf output le xfin 2 fin 2 data gnd 2 gnd 2 do 2 vp 2 MB15U36 1 20 10 11 vcc 1 ld/f out clock vcc 2 1000 pf 3v 3v .1 f .1 f .1 f .1 f 1000 pf vco notes: 1) package type: 20-pin ssop 2) clock, data, le: insert a pull-down or pull-up resistor as needed to prevent oscillation when the terminals are left open 3) the fastlock mode is controlled by the lds/fds bits and the cmc rf1 bit. when the cmc rf1 bit is set to ?h? (the rf1 charge pump current is increased 4x normal mode), the ld/fout pin (open drain output) is ?l?, enabling the parallel resistor in the loop filter. this effectively increases the lpf band width, allowing the loop to lock faster. after the loop has locked onto a new frequency, the cmc rf1 bit is set to ?l?, forcing the ld/fout output pin into a high impedance state and returning the lpf bandwidth back to its original value.
dual pll frequency synthesizer with on-chip prescaler 22 fujitsu microelectronics, inc. usage precautions to protect against damage by electrostatic discharge, note the following handling precautions: store and transport devices in conductive containers. use properly grounded workstations, tools, and equipment. turn off power before inserting or removing this device into or from a socket. protect leads with conductive sheet when transporting a board mounted device. ordering information part number package MB15U36pfv 20-pin, plastic ssop (fpt-20p-m03)
MB15U36 fujitsu microelectronics, inc. 23 package dimensions 0.500.20 (.020.008) 0.100.10(.004.004) (stand off) 0 10 details of "a" part 5.85(.230)ref 6.500.10(.256.004) * 0.650.12 5.40(.213) 4.400.10 6.400.20 nom (.252.008) (.173.004) * (.0256.0047) .006 -.001 +.002 -0.02 +0.05 0.15 .009 -.002 +.004 -0.05 +0.10 0.22 .049 -.004 +.008 -0.10 +0.20 1.25 0.10(.004) "a" index (mounting height) dimensions in mm (inches) * these dimensions do not include resin protrusion (fpt-20p-m03) 20-pin, plastic ssop
fujitsu microelectronics, inc. corporate headquarters 3545 north first street, san jose, california 95134-1804 tel: (800) 866-8608 fax: (408) 922-9179 e-mail: fmicrc@fmi.fujitsu.com web site: http://www.fujitsumicro.com ? 1999 fujitsu microelectronics, inc. all rights reserved. all company and product names are trademarks or registered trademarks of their respective owners. with respect to any information contained in this document, fujitsu makes no warranties, express, implied or otherwise, including but not limited to warranty of merchantability or of fitness for a particular purpose, or warranty that such information shall be free from errors or that such errors shall be corrected, or warranty that such information shall be free from infringement or patents, patent applications, copyrights, semiconductor chip protection rights, trade secrets and o ther proprietary or legal rights of a third party. in no event will fujitsu be responsible for any incidental or consequential damages arising out of use of this information. the information in this document does not convey any license under the copyrights, patent rights, or trademarks claimed and owned by fujitsu limited, its subsidiaries, or fujitsu microelectronics, inc. fujitsu microelectronics, inc. reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form, or by any means, or transferred to any third party without prior written consent of fujitsu microelectronics, inc. printed in u.s.a. tc-ds-20806-5/99

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